Issues: WRspice import of bsim6.1
S. R. Whiteley, Whiteley Research Inc., 4/4/2014


1.  The initial adms translation failed due to the presence of lines
of the form

Line 3873:
        CSB = CSBI - ddx((QS-QSI),V(sbulk));

where the first ddx argument is an expression, not a simple variable. 
There are a half dozen or so of these lines.  None of the publicly
available adms scripts handle this.  This is the first time I have
encountered this in Verilog-A model code.  However, according to the
Verilog-A specification, this form should be just fine.  Tiburon-based
systems apparently don't have a problem with this.

I added this capability to the WRspice adms scripts.  The other
work-around would be to modify the bsim6.va file.


2.  The initial QA run showed huge (~80%) differences in the
Idvg_core_sw CMC test (and others).

One cause of differences was found to be the setting of the GMIN
parameter.  This parameter directly affects the output in the low
sweep value range of this test.  The GMIN parameter, if not set
explicitly, will take the value of the simulator gmin.  If this does
not happen to be 1e-15, huge differences result.

In WRspice, the default gmin is 1e-12.  The CMC hspice.pm script
explicitly sets the Hspice gmin to 1e-15.  Adding similar
initialization to the wrspice.pm file fixed this issue.

Somewhere, with the QA tests, there should be a note that informs that
gmin must be set to 1e-15 for tests to succeed.  Or, one could set
GMIN explicitly in the parameters.

However, the difference reported for this CMC test was reduced to 40%,
so additional issues remained.


3.  I discovered the following.  In bsim6.0, the rdsmod parameter takes
two values 0,1 with the default and CMC runs using rdsmod=0.

  0: Internal s/d resistance model
  1: External s/d resistance model

In bsim6.1, rdsmod takes three values 0,1,2.

  0: Internal bias dependent and external bias independent s/d resistance model
  1: External s/d resistance model
  2: Internal s/d resistance model

The default is still 0, however it appears that one should choose 2 for
consistency with bsim6.0.  The CMC tests run with rdsmod=0.

With rdsmod=0, the internal source and drain nodes (si and di) are
created, and tied to source and drain effectively with
RSourceGeo or RDrainGeo resistors, which default to a milliohm.

This idiom is used frequently in bsim models (bsimsoi-4.5 has this
bug, too), and should not be.  The resulting matrix is not solvable
with standard math.  Hspice, however, does just fine with this, and I
don't know how.  Either they are using extended-precision math, or
they have an exceptional preconditioning algorithm.

One can recognize this problem as it causes the S/D swap CMC tests
to fail with significant differences.

The correct treatment of these unused internal nodes is to "collapse"
them into the source and drain nodes.  As this removes two circuit
nodes per device, it is great for efficiency.  However, it is also
necessary for accuracy and convergence in WRspice, Spice3, and
probably a large number of other simulators.

Connecting "unused" nodes with a small resistance value was necessary
in some primitive Verilog-A support where node collapsing was not
implemented.

When rdsmod=2, the si and di nodes are collapsed properly.  The qaSpec
file was modified to explicitly add this to the generated simulation
files.

This did the trick, almost.  The difference reported from the
Idvg_core_sw CMC test was reduced to 4%, which is still much larger
than one would expect.


4.  The output from the Idvg_core_sw test for bsim6.1 differs from the
similar output from bsim6.0 by 4%.  The bsim6.0 output matches the
bsim6.1 QA reference data closely.  All model parameters are the same,
with the exception of rdsmod which is 0 for bsim6.0 and (in my setup)
2 for bsim6.1.

It appears that the bsim6.1 output is wrong, but it could also be
that the bsim6.0 output, and the bsim6.1 CMC reference data, are wrong.

The difference was traced to differences in the equations between the
bsim6.0 and bsim6.1 models.  In bsim6.1 the following line

Line 3134 (bsim6.1):
 Dr = 1.0 + U0_t /(Dvsat * Dmob) * Cox * Weff / Leff * qia * Rdsi;

should be replaced with

Line 2714 (bsim6.0):
 Dr = 1.0 + U0_t * Cox * Weff / Leff * qia * Rdsi;

for consistency with bsim6.0.  With this change, agreement between
bsim6.0 and bsim6.1, and bsim6.1 and the CMC reference data, is very
close.

I'd appreciate hearing the model authors' comments on this, as I
haven't a clue which is really correct.

5, There remained very large (tens of percent) errors in most of the
AC tests.  The cause was traced to the default setting of a new CVMOD
parameter.  This parameter must be set to 1 to execute the same
initialization in the CV calculation as in bsim6.0.  Unfortunately, to
parameter does not appear in the QA parameters list, and defaults to
zero.

This gives much better agreement, but some large differences remain.
Making the code change identified in #4 above fixed many of these.   It seems
that the AC transfer is more sensitive to this than DC, changing by
10% instead of 3-4%.

There remain large differences in AV gidl tests, such as acvg_gidl_sw.
